1. Technical Field
The invention relates generally to data processing systems and, more specifically, to digital signal processing systems that determine minimum/maximum magnitude digital signal levels.
2. Background Art
In digital signal processing systems, many processing functions require determination of a minimum or maximum magnitude level signal sample in a block of signal samples. In typical digital signal processors (DSPs), the magnitude level is generally found by performing a series of instructions. This method can be very time consuming and will hinder performance of signal level determination since multiple processor execution cycles are needed to perform these instructions.
To overcome this problem, other systems developed a technique for determining the minimum, minimum magnitude, maximum, or maximum magnitude of two n-bit 2's complement operands (A and B) in one processor cycle, where n is the processor word size. The technique used the DSP arithmetic logic unit (ALU) to add or subtract (addition with 2's complementation of the B operand) the A and B operands. Then, the sign (negative or positive) of the result and the ALU overflow output is interpreted, and A or B is chosen as the subsequent output of the ALU.
Even though this system decreased the instruction path length and execution cycles per instruction of the processor, it increased the processor cycle time due to the delayed ALU result, the cycle-time limiting path of the DSP.
The reason for the delayed ALU result is twofold. First, for the minimum magnitude and maximum magnitude operations, if the ALU B operand is negative, it must be 2's complemented. That is, once the B operand has propagated to the ALU B input, its sign bit must be examined and a control signal developed that, if the sign bit is 1, causes the B operand to be 1's complemented (inverted) and incremented by 1. This increases the delay path through the ALU, because the computation cannot proceed until the control signal has been determined and applied.
Second, for all minimum or maximum operations, the ALU performs an addition and the sign bit of the result of the addition is used to select the A or B operand in lieu of the ALU result. It is known that the sign bit of the ALU result has the longest delay of any ALU result bit. Therefore, using the sign bit to select the result for a minimum or maximum operation adds further delays to the ALU result.
Other examples of data processing systems that determine the maximum/minimum numeral or signal in a series of numerals or signals, or similar ascertations, may be found in the following United States Patents which are hereby incorporated herein by reference: U.S. Pat. No. 5,072,418, "Series Maximum/Minimum Function Computing Devices, Systems and Methods," (issued December 1991 to Boutaud et al and assigned to Texas Instruments Inc.); U.S. Pat. No. 4,567,572, "Fast Parallel Sorting Processor," (issued January 198 to Morris et al and assigned to N.S.A.); U.S. Pat. No. 4,774,688, "Data Processing System for Determining Min/Max in a Single Operation Cycle as a Result of a Single Instruction," (issued September 1988 to Kobayashi et al and assigned to IBM Corp); U.S. Pat. No. 4,998,219, "Method and Apparatus for Determining the Greatest Value of a Binary Number and for Minimizing Any Uncertainty Associated with the Determination," (issued March 1991 to Frauenglass and assigned to AIL, Systems, Inc); U.S. Pat. No. 4,856,029, "Technique for Processing a Digital Signal Having a Zero Overhead Sync," (issued August 1989 to Geyer et al and assigned to Eastman Kodak Co.); U.S. Pat. No. 5,262,969, "Arrangement and Method of Ascertaining Data Word Number of Maximum or Minimum in a Plurality of Data Words," (issued November 1993 to Ishihara and assigned to NEC Corp.); U.S. Pat. No. 4,734,876, "Circuit for Selecting One of a Plurality of Exponential Values to a Predetermined Base to Provide a Maximum Value," (issued March 1988 to Williams and assigned to Motorola, Inc.); U.S. Pat. No. 5,187,675, "Maximum Search Circuit," (issued February 1993 to Dent et al and assigned to Ericsson-GE Mobile Communications Holding Inc.); and U.S. Pat. No. 4,539,549, "Method and Apparatus for Determining Minimum/Maximum of Multiple Data Words," (issued September 1985 to Hong et al and assigned to IBM Corp.).
Although each aforementioned patent provides a way to determine the maximum/minimum resultant numeral, they either are not able to do it within the ALU, and subsequently, the performance time of the system is increased, or they do not perform with maximum/minimum magnitude operations.